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i.MX53 Layout Recommendations
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 2-3
2.1.1 Fanout
Figure 2-3 shows the fanouts for the i.MX53 for two different layers.
Figure 2-3. i.MX53 Fanouts
The fanout scheme creates a four quadrant structure that facilitates the placement of decoupling capacitors
on the bottom side of the PCB. This keeps them closer to the power balls, which is critical for minimizing
inductance and ensuring high-speed transient current demand by the processor.
A correct via size is critical for preserving adequate routing space. The recommended geometry for the via
pads is: pad size 16 mils and drill 8 mils.
The constraints for the trace size may depend on a number of factors, such as the board stackup and
associated di-electric and copper thickness, required impedance, and required current (for power traces).
On the Freescale reference design, the minimum trace width of 3 mils is used for the DDR routing.
- User’s Guide 1
- Document Number: MX53UG 2
- Rev. 1, 3/2011 2
- How to Reach Us: 2
- Contents 10
- Freescale Semiconductor xi 11
- Freescale Semiconductor xiii 13
- Number Title 14
- Freescale Semiconductor xiv 15
- About This Guide 17
- Organization 18
- Essential Reference 19
- Signal Conventions 20
- Acronyms and Abbreviations 20
- Hardware Design and Bring-up 25
- I-2 Freescale Semiconductor 26
- Chapter 1 27
- Design Checklist 27
- 1.2 DDR Reference Circuit 34
- 1.3 Avoiding I 35
- C Conflicts 35
- 1.4 JTAG Signal Termination 36
- Chapter 2 37
- 2-2 Freescale Semiconductor 38
- 2.1.1 Fanout 39
- 2.2 Stackup 40
- Freescale Semiconductor 2-5 41
- 2.5 Routing Topologies 43
- 2.5.1 1 Gbyte Topologies 44
- 2.5.2 2 Gbyte Topologies 45
- 2-10 Freescale Semiconductor 46
- Freescale Semiconductor 2-11 47
- 2.5.3 DDR2 Routing Examples 48
- Freescale Semiconductor 2-19 55
- 2.6 Power Recommendations 62
- 2.8 SATA Recommendations 63
- 2.9 LVDS Recommendations 63
- 2.10 Reference Resistors 64
- Freescale Semiconductor 2-29 65
- 2-30 Freescale Semiconductor 66
- Chapter 3 67
- Understanding the IBIS Model 67
- 3.2 Header Information 68
- 3.4 Model Information 70
- 3-6 Freescale Semiconductor 72
- 3.5 Model Golden Waveforms 73
- 3.6.1 [Model Selector] ddr 74
- 3.6.2 [Model Selector] gpio 74
- 3.6.3 [Model Selector] lvio 75
- 3.6.4 [Model Selector] uhvio 75
- 3.8 References 77
- 3-12 Freescale Semiconductor 78
- Chapter 4 79
- Using the IOMUX Design Aid 79
- 4-2 Freescale Semiconductor 80
- Freescale Semiconductor 4-3 81
- 4-4 Freescale Semiconductor 82
- Freescale Semiconductor 4-5 83
- 4-6 Freescale Semiconductor 84
- Freescale Semiconductor 4-7 85
- 4-8 Freescale Semiconductor 86
- Freescale Semiconductor 4-9 87
- 4-10 Freescale Semiconductor 88
- Freescale Semiconductor 4-11 89
- 4-12 Freescale Semiconductor 90
- 4.5 IOMUX Features Guide 91
- 4.5.2.1 File Menu 92
- 4.5.2.2 Device Menu 93
- 4.5.2.3 View Menu 93
- 4.5.2.4 Help Menu 94
- 4.5.5.1 Signals Tab 94
- 4.5.5.2 Ball Diagram Tab 95
- 4-18 Freescale Semiconductor 96
- Chapter 5 97
- Figure 5-1. Internal LDOs 98
- VB UCKC OR E 99
- Setting up Power Management 100
- Figure 5-3. Power Connections 102
- DA9053 103
- Figure 5-3 and Figure 5-4 104
- 5.3.1 Using the I 105
- C Interface 105
- 5.4 Interface Table 106
- NVCC_EIM_DRAM 108
- Freescale Semiconductor 5-13 109
- LTC3589-1 110
- Optional 110
- Freescale Semiconductor 5-15 111
- 5-16 Freescale Semiconductor 112
- 5.6.1 DA9053 113
- 5-18 Freescale Semiconductor 114
- 5.6.2 LTC3589-1 116
- 9729 117
- 5-22 Freescale Semiconductor 118
- Chapter 6 119
- Processor 119
- 6-2 Freescale Semiconductor 120
- 6.2 i.MX53 Memory Interface 121
- 6.5.1 Main Control Register 128
- 6.5.2 Power Down Register 129
- 31 29 28 26 25 21 20 16 130
- 15 14 12 11 9 8 5 4 3 2 0 130
- 6-14 Freescale Semiconductor 132
- Chapter 7 133
- 7.4 Avoiding Reset Pitfalls 134
- Chapter 8 137
- Freescale Semiconductor 8-3 139
- 8-4 Freescale Semiconductor 140
- Chapter 9 141
- 9-2 Freescale Semiconductor 142
- 4. Save the configuration 143
- 9-4 Freescale Semiconductor 144
- Software Development 145
- II-2 Freescale Semiconductor 146
- Chapter 10 147
- 10.2.2 DDR Test 148
- 10.2.9 SPI-NOR Test 150
- Chapter 11 151
- 11-6 Freescale Semiconductor 156
- Chapter 12 157
- Porting the Android Kernel 157
- 12-2 Freescale Semiconductor 158
- 12.3 Initializing Android 160
- Figure 12-3. Linux Kernel 161
- 12-6 Freescale Semiconductor 162
- Chapter 13 163
- 13.2.1 Defining the Pads 164
- 13.2.3 Example—Setting a GPIO 165
- 13.3.2 Machine Layer File 167
- 13.3.3 Example—Setting a GPIO 167
- • 0x294—MUX Control Offset 168
- • 0—Select Input 168
- Chapter 14 169
- Registering a New UART Driver 169
- 14.3 Testing the UART 170
- 14.4 File Names and Locations 170
- 14-4 Freescale Semiconductor 172
- Chapter 15 173
- Table 15-2. ESDHC Pins 178
- 15.3.3 Interface Layouts 179
- 15-8 Freescale Semiconductor 180
- Chapter 16 181
- (MTD) Driver 181
- .size = 0x000100000 182
- Table 16-3. CSPI Parameters 183
- 16.5 Hardware Operation 184
- 16.6 Software Operation 185
- 16-6 Freescale Semiconductor 186
- Chapter 17 187
- 17.2 Creating a Custom Keymap 188
- 17.4 Enabling the Keypad 189
- 17.5 Testing the Keypad 189
- Chapter 18 191
- Figure 18-2. Interface 194
- Table 18-2. Timing Parameters 194
- Parameters 198
- Table 18-7. Sample Values 199
- CLAA057VA01CT LCD 204
- 18-16 Freescale Semiconductor 206
- Chapter 19 207
- 19.2.2 Programming Interface 208
- 19.3 LDB Ports 209
- 19.4 Further Reading 210
- Chapter 20 211
- 20.5 Using the I 216
- Package List > imx-test 219
- Figure 20-3. Chessboard Test 219
- 20-10 Freescale Semiconductor 220
- Freescale Semiconductor 20-11 221
- 20-14 Freescale Semiconductor 224
- Chapter 21 225
- 21-4 Freescale Semiconductor 228
- Chapter 22 229
- 22.2 Source Code 230
- 22.3 Ethernet Configuration 230
- Chapter 23 231
- Porting USB Host1 and USB OTG 231
- 23-2 Freescale Semiconductor 232
- Appendix A 233
- Revision History 233
- A-4 Freescale Semiconductor 234
- Freescale Semiconductor A-5 235
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